1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to densely packed standard cells for integrated circuit products and methods of making such products.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive currents than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
By using such field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, embedded memories and the like. Over the recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation and the “packing density” in such products has been increased over the recent years. i.e., there are an increased number of devices per unit area. Such improvements in the performance of transistor devices has reached the point where the limiting factor of the ultimate operating speed of complex integrated circuit products is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the semiconductor-based circuit elements. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end that is connected to a respective metal line in the metallization layer. In some applications, the second end of the contact structure may be connected to a contact region of a further semiconductor-based circuit element, in which case the interconnect structure in the contact level is also referred to as a local interconnect. The contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. As the critical dimensions of the circuit elements in the device level decreased, the dimensions of metal lines, vias and contact elements were also reduced. In some cases, the increased packing density has mandated the use of sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required packing density in accordance with the density of circuit elements in the device level.
As device dimensions have decreased, e.g., transistors with gate lengths of 50 nm and less, the contact elements in the contact level have to have critical dimensions on the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions is 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy.
As device dimensions have continued to shrink over recent years, it is becoming more challenging to accurately and repeatedly manufacture integrated circuit products that meet performance criteria established for such integrated circuit products. Typically, semiconductor devices are formed on discrete islands of semiconducting substrate, i.e., active regions that are defined in the substrate by isolation structures. For example, FIGS. 1A-1B depict illustrative prior art standard cell pairs 10 and various conductive structures formed to establish electrical contact to source/drain regions. The illustrative prior art device is generally comprised of a so-called “top cell” and a “bottom cell”. The standard cell pair 10 is intended to be representative in nature. For example, in one illustrative example, the top cell may be part of a combinational or sequential circuit and the bottom cell may also be part of a combinational or sequential circuit, etc. Examples of such combinational circuits include NAND, NOR, and inverter circuits, etc., while examples of sequential circuits include Scan FLOP, MUX, etc.
With continuing reference to FIG. 1A, the standard cell 10 is comprised of a plurality of spaced apart active regions 12A, 12B, 12C and 12D that are defined in a semiconductor substrate by one or more isolation structures, represented by the space between the active regions 12A-D. Semiconductor devices of different conductivity type may be formed above each of the active regions 12A-12D. For example, P-type devices may be formed in the active regions 12A, 12D, while N-type devices may be formed in the active regions 12B, 12C. In the depicted example, the transistor devices are FinFET type devices that are comprised of a plurality of fins 16. Of course, the number of fins may vary depending upon the particular application. In the depicted example, the devices formed above the active regions 12A-12B share a common gate structure 14A (gate electrode and gate insulation layer) while the devices formed above the active regions 12C-12D share a common gate structure 14B. Sidewall spacers that are typically formed adjacent the gate structures 14A, 14B are not depicted in the attached drawings. All of the devices have illustrative source/drain regions 18 formed in the fins 16. The source/drain regions 18 are formed by performing one or more ion implantation processes on the fins 16 after the gate structures 14A, 14B are formed. In the depicted example, the fins 16 are depicted as fins that have not been subjected to a so-called fin merger process whereby additional semiconductor material is formed on the fins 16 after the gate structures 14A, 14B are formed so as to hopefully provide a larger surface to which electrical contact can be made to the source/drain regions 18.
Also depicted in FIGS. 1A-1B are a plurality of conductive structures 20A-D and 22A-D that are formed to establish electrical contact to the source/drain regions 18. The reference numbers 20 and 22 may be used to generally refer to the conductive structures 20A-D and 22A-D, respectively. Reference FIG. 1B is a cross-sectional view of one illustrative embodiment of the conductive structures 20A, 22A taken where indicated in FIG. 1A. The conductive structures 20, 22 will have the same configuration on all of the devices. FIG. 1B also depicts an illustrative isolation structure 24 and a plurality of layers of insulating material 26, 28 and 30 that are formed above the active region 12A. The insulating materials 26, 28 and 30 are not depicted in the plan view shown in FIG. 1A so as to facilitate explanation of the device 10. In general, with reference to FIG. 1B, after the source/drain regions 18 are formed in the fins 16, the layer of insulating material 26 is deposited and a planarization process may then be performed on the layer of insulating material 26. Thereafter, the conductive structures 20A-D may be formed by depositing a layer of conductive material, e.g., tungsten, and thereafter patterning the deposited layer of conductive material to define the conductive structures 20A-D shown in FIG. 1A. The layer of insulating material 28 may then be deposited on the device and planarized. In some cases, the conductive structures 20 may be referred to within the industry as a so-called “trench silicide” structure. After the layer of insulating material 28 is planarized, the conductive structures 22A-D may be formed by depositing a layer of conductive material, e.g., tungsten, and thereafter patterning the deposited layer of conductive material to define the conductive structures 22A-D shown in FIG. 1A. The layer of insulating material 30 may then be deposited on the device and planarized. In some cases, the conductive structures 22 may also be referred to within the industry as a “CA contact.”
FIG. 1C is a cross-sectional view taken through the middle fin 16 and the active region 12A, as indicated in FIG. 1A. The purpose of FIG. 1C is to show the stacking arrangement of various conductive structures that are formed to establish electrical contact to the FinFET device, and particularly to the source/drain regions 18 of the device. Various layers of insulating material that are formed to electrically insulate the various conductive structures are not depicted in FIG. 1C. The gate structure 14A is depicted as having an illustrative gate insulation layer 14X and gate electrode 14Y. Also depicted in FIG. 1C is an illustrative gate contact 23 that is conductively coupled to the gate structure 14A. The gate contact 23 is sometimes referred to within the industry as a “CB” contact. The gate contact 23 is typically formed after the formation of the conductive structures 22 using known processing techniques.
To establish electrical connection to the FinFET devices formed on the substrate, a plurality of stacked metallization layers are formed above the substrate. Essentially, these metallization layers constitute the electrical “wiring” that is used to electrically couple the circuits and devices formed on the substrate to one another so as to form a functional integrated circuit product. For example, a modern integrated circuit product may contain 7-10 or more metallization layers. The metallization layers are typically comprised of a plurality of conductive lines that are routed as needed so as to provide within-level or intra-level conductivity. The metallization layers are coupled to one another by a plurality of conductive structures, known as vias, that are typically formed in a separate layer of insulating material so as to provide electrical conductivity between metallization layers. The very first general metallization layer on an integrated circuit product is typically referred to within the industry as the “metal-1” or “M1” layer. The first via layer is typically referred to within the industry as the “via-zero” or “V0” layer. The V0 layer contains a plurality of conductive via structures that are used to establish electrical contact between the semiconductor devices/circuits formed in the substrate and the M1 layer. The conductive via structures may be formed in a variety of different configurations, cylindrical or square-shaped plugs, short line-type segments, etc. FIG. 1C depicts the V0 and M1 layers, which are not depicted in FIGS. 1A-1B so as to not complicate the discussion herein. As depicted in FIG. 1C, the conductive vias in the V0 layer are conductively coupled to the conductive structures 22 and the gate contact 23. The manner in which the conductive lines and vias are formed are well known to those skilled in the art.
With continuing reference to FIG. 1C, note that there are two separate conductive structures—the conductive structures 20A and 22A that are positioned between the V0 layer and the source drain regions 18. That is, this prior art technique required the formation of two separate conductive structures in order to establish electrical contact between the V0 layer and the source/drain regions 18. The combined height 50 of these two conductive structures (20A and 22A) may vary depending upon the particular application. In one illustrative embodiment, using current day technology, the combined thickness may be on the order of about 50-60 nm.
FIGS. 2A-2H depict one illustrative prior art method of forming the prior art standard cell 10 depicted in FIGS. 1A-1C. In FIGS. 2A-2H, the various layers of insulating material are not depicted in the plan drawings so as to facilitate explanation of one illustrative manner in which the device 10 may be formed.
FIG. 2A depicts the device 10 at a point in fabrication wherein active regions 24 (see FIG. 2B) have been formed in the substrate to define the active regions 12A-12D. The schematically depicted fins 16 and the gate structures 14A, 14B have also been formed at this point in the process flow. The fins 16 are typically formed by performing one or more etching processes to form a plurality of fin-formation trenches (not shown) in the substrate to define the fins 16. Thereafter, an insulating material is deposited so as to overfill the fin-formation trenches and a recess etching process is performed on the insulating material to reduce its thickness, which results in the formation of isolation regions (not shown) at the bottom of the fin-forming trenches. This recessing process typically exposes the fins 16 to the final desired fin height. After the fins 16 are formed, the schematically depicted gate structures 14A, 14B are formed. The gate structures 14A, 14B are typically comprised of a gate insulation material and one or more gate electrode materials. The gate structures 14A, 14B may be formed using so-called “gate-first” or “replacement-gate” techniques. In one particular example, the gate structures 14A, 14B may initially be formed by depositing the layers of the appropriate materials such that they cover all of the active areas 12A-D and the isolation materials therebetween and then patterning the layers of materials using a first gate etch masking layer (not shown) to define a single line of gate electrode material that spans across all of the active regions 12A-D. Thereafter, the first gate etch masking layer is removed and a second gate etch masking layer (not shown) is used to cut the single line of gate electrode material in the region indicated by the dashed lines 15 so as to thereby result in the depicted gate structures 14A, 14B. This second gate etch mask is sometimes referred to as a “gate-cut” mask. Thereafter, the source/drain regions 18 are formed by performing one or more ion implantation processes on the fins 16 after the gate structures 14A, 14B are formed. Sidewall spacers (not shown) may also be formed adjacent the gate structures 14A, 14B as part of the process of forming the source/drain regions 18. Of course, various masking layers will be used during the ion implantation processes to expose the fins where ions are to be implanted while covering other fins on different device types. In general, with reference to FIG. 2B, after the source/drain regions 18 are formed in the fins 16, the layer of insulating material 26 is deposited so as to overfill the fin-formation trenches and a planarization process may then be performed on the layer of insulating material 26.
With reference to FIG. 1A, tip-to-tip spacing 31 between the conductive features 20 is very small and typically exceeds what can be directly patterned using a single patterned etch mask layer with existing photolithography equipment. Thus, the four illustrative conductive structures 20A-D are formed using a double patterning technique that involves two separate masking-patterning operations. For example, as shown in FIG. 2C, the spaced-apart conductive structures 20A and 20C have been formed above the active regions 12A, 12C by performing a first deposition/masking/etching process. The tip-to-tip spacing 33 between the spaced-apart conductive structures 20A and 20C is large enough so that the structures 20A, 20C can be readily patterned using a single etch mask layer. FIG. 2D is a cross-sectional view that shows the formation of the illustrative conductive structures 20A above the active region 12A at this point in the process flow. Similar conductive structures 20C are formed above the active region 12C at this time as well. FIG. 2E is a cross-sectional view that shows the absence of the conductive structures 20D that will ultimately be formed above the active region 12D at this point in the process flow. Note the absence of the conductive structures 20B (that will eventually be formed above the active region 12B) at this point in the process flow as well.
As shown in FIG. 2F a second deposition/masking/etching process sequence is performed to form the spaced-apart conductive structures 20B and 20D above the active regions 12B, 12D. The tip-to-tip spacing 35 between the spaced-apart conductive structures 20B and 20D is large enough so that the structures 20B, 20D can be readily patterned using a single masking layer. FIG. 2G is a cross-sectional view that shows the formation of the illustrative conductive structures 20D above the active region 12D at this point in the process flow. Similar conductive structures 20B are formed above the active region 12B at this time as well. Thus, at this point in the process flow, two separate etch mask layers were required to form the conductive structures 20A-D due to the tight tip-to-tip spacing between the structures 20A-20D. At this point, the layer of insulating material 28 (see FIG. 1B) may be deposited on the device 10 and planarized.
As shown in FIG. 2H, the next process operation involves the formation of the conductive structures 22 on the device 10. The tip-to-tip spacing 32 between the conductive structures 22, while small, is still large enough to permit forming all eight of the illustrative conductive structures 22 shown in FIG. 2H by performing a single deposition/masking/etching process sequence using a single masking layer. At this point, the layer of insulating material 30 (see FIG. 1B) may be deposited on the device 10 and planarized.
Thus, using the above-described prior art technique, at this stage, three separate masking layers were required to form the conductive structures 20, 22 on the product 10: the two masking layers used in forming the conductive structures 20A-D and the single masking layer used in forming the conductive structures 22A-D.
The present disclosure is directed to densely packed standard cells for integrated circuit products and methods of making such products that may avoid, or at least reduce, the effects of one or more of the problems identified above.